This information is intended to clear up any confusion about differential signaling. Differential signaling has evolved into the primary method for connecting logic components and products together. It has replaced most of the parallel bus architectures such as PCI. Because differential signaling has become the protocol of choice for nearly all new designs it is important to understand how it operates and what design considerations are important and which are not. Unfortunately, there are a very large number of misconceptions about how this protocol operates and which rules in circulation are valid and which are not.
Failing to understand which rules are valid may result in designs that are excessively complex or may not work properly. This chapter is intended to clear up any confusion about differential signaling. To make appropriate design decisions it is important to understand how differential signaling operates. Figure 4. It is made up of two boxes or chassis, Box A and Box B. These two have their logic grounds connected with a path that has a DC offset too large for single-ended logic to properly operate.
In Box A, the single-ended logic signal is converted into two signals A and A-. These are identical signals one the exact inverse of the other. What they have in common is that they are tightly timed to each other such that when a logic state change takes place the two cross in the middle, half way between a logic 1 and a logic 0.
This is achieved by sending each of the signals on a parallel terminated transmission line, each usually 50 ohms and both the same electrical length. Note that there is no differential impedance involved. A good question might be how the industry came to think that differential impedance mattered.
This will be answered later. The emitter coupled pair of transistors in box B is more commonly called a current switch. Its task is to steer the current, I, up one side of the pair of the other. When the current is going up one side this represents a logic 1 and when it goes up the other side a logic 0. When the two signals, A and A-, switch logic states the voltages on the bases of the two transistors reverse and the current changes sides denoting a logic state change. So, the circuit in box B is a crossing detector.
Preserving the accuracy of the crossing is the dominating problem when engineering a differential pair path. More on this later. The reason for using differential signaling is the fact that the grounds in the two boxes are too far apart to permit reliable single-ended logic operation.
Compensating for the DC offset between the two ends of the logic path is achieved by the fact that the two transistor emitters in box B are sitting on a current source, I, that allows them to move up and down as box A moves up and down. The collectors of the two transistors in box B are also current sources. Thus, the two transistors in the box B, the current switch, can move up and down with box A over a wide voltage range successfully dealing with the DC offsets and delivering a valid logic signal to box B.
With wired Ethernet, this DC offset problem is solved by using transformers at each end of the twisted pair that connects the two boxes. Notice in Figure 4.
Each is parallel terminated in the impedance of that transmission line, usually 50 ohms. Neither one of these transmission lines knows the other exists and can do its job independent of what is happening on the other line. A good question is where the idea that a differential impedance was necessary or why tightly coupling these two lines to each other was important came from. Notice that there is a Vref to which each of the parallel terminations are connected. When one side is at the logic high or 1 and the other is at a logic low or 0, the net current into or out of Vref is zero so long as the two signals cross in the middle as they were designed to do.
Under these conditions the conclusion was drawn correctly that this connection was not required and was omitted in most designs resulting in two ohm resistors connected in series. It seemed logical to replace these with a single ohm resistor, hence the notion that a ohm differential impedance was required. This arrangement ceases to be acceptable when data rates are very high, such as 2.
If there is no misalignment of the two edges skew the circuit works fine. As soon as the two edges become misaligned in time they no longer cross in the middle and some current needs to flow into or out of Vref. If the Vref connection is missing the edges are eroded resulting in performance degradation.
From either Figure 4. In almost all cases these lines will be ohms. In the case of classical LVDS, the designer must place the terminating resistors at or after the last load.
If there is no Vref termination voltage, a single ohm resistor across the input to the receiver will be good enough. Several of the protocols listed at the start of this chapter recommend an impedance other than ohm differential of ohm single ended transmission lines. For example, LVDS specifies 93 ohms differential or If the bulk of a design is 50 ohms, and most will be, this forces the stack up design to accommodate two different impedances, which is not desirable. By examining all these protocols, the author has determined that all of them, including DDR data and clock lines will work properly with ohm lines.
Therefore, it is not necessary to have two different impedances in the same stackup, thereby simplifying routing. In some conferences it has been said that tight coupling is a good thing to do. The usual reason given is that this provides common mode noise rejection.
These transmission lines are in a layer called offset stripline. This is not common mode rejection. For there to be common mode rejection the field strength of the inducing signal would need to be the same intersecting both members of the differential pair. This is not achievable with traces in a PCB. Designers counting on this may find they have a severe crosstalk problem.
Since common mode noise rejection cannot be achieved in a PCB, what a designer must do is assume that each member of a differential pair is a single-ended trace and make sure that there is enough space between it and any other signals that might cause a crosstalk problem.
Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC industry standard. To validate the integrity of PCB assembly, circuit board manufacturers rely on automated circuit board testing systems. Choosing the best-priced components to use on your circuit board can save you a lot of money as long as you look at component cost volume analysis first.
With rising circuit speeds and increased noise and interference, PCB layout designers can no longer afford to ignore PCB impedance control. PCB designers should understand these high-speed analog layout techniques for the best results when designing mixed-signal circuit boards.
To ensure layout success, it is essential for circuit designers to fully use their PCB design rules for digital circuits. The best PCB thermal relief guidelines should be used to create dependable connections both electrically and for manufacturability.
Depending on the nature of their application, flexible printed circuits have unique requirements for footprints. Understanding PCB grounding techniques can help a designer lay out a circuit board with better signal and power integrity. For the best board layouts, you should follow a comprehensive set of PCB via size guidelines that adhere to standards and support your other design decisions.
For circuit board designs that perform well and can be manufactured without errors, follow these PCB component placement tolerances. The receiver has a differential amplifier that receives the signal as the difference in voltages it sees on the two wires.
Theoretically, there is no total current flow in the twisted pair of a differential signal because the amplitudes cancel each other out. This means that ground is less important, but most communication using differential pairs will include a ground wire to maintain a reference to refrain from having signals go beyond specified boundaries.
Signals are not subject to local ground disturbances when passing from one PCB to another, for example. Current flows in opposite directions through the differential pair rather than a ground wire; current does not flow to ground ideally. Since currents flow in opposite directions in a differential signal pair, the magnetic flux gets cancelled and EMI noise from signal harmonics is lower.
In the above diagram, the black line shows the signal and the red line shows the complementary opposite signal. When the signal gets transmitted, any external noise will affect both wires equally in the differential pair. The difference amplifier on the receiving end rejects common signals, so noise riding the signals can be identified and rejected.
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